Let us next consider the various techniques for microstructural examination.
It is usually necessary to prepare a section of a material in order to study the
size, shape and distribution of crystals within it. In the case of metallic
materials, this is referred to as metallographic examination (‘materialography’
is sometimes used more generally), and great precautions have to be taken at
every stage to ensure that the method of preparation does not itself alter the
microstructure originally present.
If the section for study is cut from the bulk by milling or sawing, or by the
use of an abrasive cutting wheel, ample cooling and lubrication has to be
provided to prevent its temperature from rising. Gross distortions from the
cutting process are eliminated by grinding the surface with successively
finer abrasives such as emery or silicon carbide. If the grains are coarse
enough to be seen with the naked eye, one can at this stage prepare the
surface for macroscopic examination.
The surface of the specimen is etched, usually in a dilute acid, by immersing
it or swabbing it until the individual grains are revealed. Because of the
different rates of chemical attack along different planes in a crystal, when
the surface is etched, crystallographic terraces are formed upon each grain
and these reflect light in directions which vary with the orientation of the
grain, so that some crystals appear light and some dark. The macrostructure
of a piece of cast metal which has been prepared in this way
A much lighter etching treatment is applied for microscopical examination
than for macro-studies. With some etching reagents and very short etching
times, metal is dissolved only at the grain boundaries, giving rise to shallow
grooves there, which are seen as a network of dark lines under the microscope.
A reflecting optical microscope may give magnifications of over 1000 ×,
with a resolution of about 1 ìm. The upper limit of magnification of the
optical microscope is often inadequate to resolve structural features which
are important in engineering materials, however, and electron microscopy is
widely employed for this purpose. Field-ion microscopy is a research tool
with a resolving power that permits the resolution of the individual atoms in
crystals and these can be identified by use of the atom-probe technique.
Saturday, May 2, 2009
Crystal structure
Crystal structure refers to the ordering of atoms into different crystalline
arrangements. It is the arrangement of these atoms – the strength and
directionality of the interatomic bonds – which determines the ultimate strength
of the solid. Techniques involving X-ray or electron diffraction are employed
to determine crystal structures, and four types of interatomic bonding are
recognized: van der Waals, covalent, ionic and metallic. The latter three
‘primary’ bonds are limiting cases, however, and a whole range of intermediate
bonding situations also exist in solids.
The van der Waals force is a weak ‘secondary’ bond and it arises as a
result of fluctuating charges in an atom. There will be additional forces if
atoms or molecules have permanent dipoles as a result of the arrangement of
charge inside them. In spite of their low strength, these forces can still be
important in some solids; for example it is an important factor in determining
the structure of many polymeric solids.
Many common polymers consist of long molecular carbon chains with
strong bonds joining the atoms in the chain, but with the relatively weak van
der Waals bonds joining the chains to each other. Polymers with this structure
are thermoplastic, i.e. they soften with increasing temperatures and are readily
deformed, but on cooling they assume their original low-temperature properties
and retain the shape into which they were formed.
The essential feature of a covalent bond is the sharing of electrons between
atoms, enabling them to attain the stable configuration corresponding to a
filled outermost electron shell. Thus, an atom with n electrons in that shell
can bond with only 8 – n neighbours by sharing electrons with them.
For example, when n = 4, as in carbon in the form of diamond, one of the
hardest materials known, each atom is bonded equally to four neighbours at
the corners of a regular tetrahedron and the crystal consists of a covalent molecule.
The elements can be divided into two classes, electronegative elements
(such as oxygen, sulphur and the halogens) that tend to gain a few electrons
to form negatively charged ions with stable electron shells, and electropositive
elements (such as metals) that easily dissociate into positive ions and free
electrons. Ionic bonding consists of an electrostatic attraction between positive
and negative ions. If free atoms of an electropositive element and an
electronegative element are brought together, positive and negative ions will
be formed which will be pulled together by electrostatic interaction until the
electron clouds of the two ions start to overlap, which gives rise to a repulsive
force. The ions thus adopt an equilibrium spacing at a distance apart where
the attractive and repulsive forces just balance each other.
arrangements. It is the arrangement of these atoms – the strength and
directionality of the interatomic bonds – which determines the ultimate strength
of the solid. Techniques involving X-ray or electron diffraction are employed
to determine crystal structures, and four types of interatomic bonding are
recognized: van der Waals, covalent, ionic and metallic. The latter three
‘primary’ bonds are limiting cases, however, and a whole range of intermediate
bonding situations also exist in solids.
The van der Waals force is a weak ‘secondary’ bond and it arises as a
result of fluctuating charges in an atom. There will be additional forces if
atoms or molecules have permanent dipoles as a result of the arrangement of
charge inside them. In spite of their low strength, these forces can still be
important in some solids; for example it is an important factor in determining
the structure of many polymeric solids.
Many common polymers consist of long molecular carbon chains with
strong bonds joining the atoms in the chain, but with the relatively weak van
der Waals bonds joining the chains to each other. Polymers with this structure
are thermoplastic, i.e. they soften with increasing temperatures and are readily
deformed, but on cooling they assume their original low-temperature properties
and retain the shape into which they were formed.
The essential feature of a covalent bond is the sharing of electrons between
atoms, enabling them to attain the stable configuration corresponding to a
filled outermost electron shell. Thus, an atom with n electrons in that shell
can bond with only 8 – n neighbours by sharing electrons with them.
For example, when n = 4, as in carbon in the form of diamond, one of the
hardest materials known, each atom is bonded equally to four neighbours at
the corners of a regular tetrahedron and the crystal consists of a covalent molecule.
The elements can be divided into two classes, electronegative elements
(such as oxygen, sulphur and the halogens) that tend to gain a few electrons
to form negatively charged ions with stable electron shells, and electropositive
elements (such as metals) that easily dissociate into positive ions and free
electrons. Ionic bonding consists of an electrostatic attraction between positive
and negative ions. If free atoms of an electropositive element and an
electronegative element are brought together, positive and negative ions will
be formed which will be pulled together by electrostatic interaction until the
electron clouds of the two ions start to overlap, which gives rise to a repulsive
force. The ions thus adopt an equilibrium spacing at a distance apart where
the attractive and repulsive forces just balance each other.
Evolution of the Microprocessor
The Intel Corporation is generally acknowledged as the company that introduced the
first microprocessor successfully into the marketplace. Its first processor, the 4004, was
introduced in 197 1 and evolved from a development effort while making a calculator chip
set. The 4004 microprocessor was the central component in the chip set, which was called
the MCS-4. The other components in the set were a 4001 ROM, a 4002 RAM, and a 4003
shift register.
Shortly after the 4004 appeared in the commercial marketplace, three other
general-purpose microprocessors were introduced: the Rockwell International 4-bit PPS-4,
the Intel 8-bit 8008, and the National Semiconductor 16-bit IMP-16. Other companies,
such as General Electric, RCA, and Viatron, also made contributions to the development of
the microprocessor prior to 197 1.The microprocessors introduced between 197 1 and 1972 were the first-generation systems designed using PMOS technology. In 1973, second-generation microprocessors such as the Motorola 6800 and the Intel 8080 (8-bit microprocessors) were introduced.The second-generation microprocessors were designed using NMOS technology. This
technology resulted in a significant increase in instruction execution speed over PMOS and
higher chip densities. Since then, microprocessors have been fabricated using a variety of
technologies and design.
NMOS microprocessors such as the Intel 8085, the Zilog 280,
and the Motorola 6800/6809 were introduced based on second-generation microprocessors.
A third generation HMOs microprocessor, introduced in 1978 is typically represented by
the Intel 8086 and the Motorola 68000, which are 16-bit microprocessors.
During the 1980’s, fourth-generation HCMOS and BICMOS (a combination of
bipolar and HCMOS) 32-bit microprocessors evolved. Intel introduced the first commercial
32-bit microprocessor, the problematic Intel 432, which was eventually discontinued.
Since 1985, more 32-bit microprocessors have been introduced. These include Motorola’s
68020, 68030, 68040, 68060, PowerPC, Intel’s 80386, 80486, the Intel Pentium family,
Core Duo, and Core2 Duo microprocessors..
The performance offered by the 32-bit microprocessor is more comparable to
that of superminicomputers such as Digital Equipment Corporation’s VAX11/750 and
VAX11/780. Intel and Motorola also introduced RISC microprocessors: the Intel 80960
and Motorola 88 100/PowerPC, which had simplified instruction sets. Note that the purpose
of RISC microprocessors is to maximize speed by reducing clock cycles per instruction.
Almost all computations can be obtained from a simple instruction set. Note that, in order
to enhance performance significantly, Intel Pentium Pro and other succeeding members of
the Pentium family and Motorola 68060 are designed using a combination of RISC and
CISC.of the Motorola 68XXX and PowerPC microprocessors will
be provided next. Motorola’s 32-bit microprocessors based on the 68000 (16-bit
microprocessor) architecture include the MC68020, MC68030, MC68040, and MC68060.
Table 1.1 compares the basic features of some of these microprocessors with the 68000.
MC68020 is Motorola’s first 32-bit microprocessor. The design of the 68020 is
based on the 68000. The 68020 can perform a normal read or write cycle in 3 clock cycles
without wait states as compared to the 68000, which completes a read or write operation in
4 clock cycles without wait states. As far as the addressing modes are concerned, the 68020
includes new modes beyond those of the 68000. Some of these modes are scaled indexing,
larger displacements, and memory indirection.
first microprocessor successfully into the marketplace. Its first processor, the 4004, was
introduced in 197 1 and evolved from a development effort while making a calculator chip
set. The 4004 microprocessor was the central component in the chip set, which was called
the MCS-4. The other components in the set were a 4001 ROM, a 4002 RAM, and a 4003
shift register.
Shortly after the 4004 appeared in the commercial marketplace, three other
general-purpose microprocessors were introduced: the Rockwell International 4-bit PPS-4,
the Intel 8-bit 8008, and the National Semiconductor 16-bit IMP-16. Other companies,
such as General Electric, RCA, and Viatron, also made contributions to the development of
the microprocessor prior to 197 1.The microprocessors introduced between 197 1 and 1972 were the first-generation systems designed using PMOS technology. In 1973, second-generation microprocessors such as the Motorola 6800 and the Intel 8080 (8-bit microprocessors) were introduced.The second-generation microprocessors were designed using NMOS technology. This
technology resulted in a significant increase in instruction execution speed over PMOS and
higher chip densities. Since then, microprocessors have been fabricated using a variety of
technologies and design.
NMOS microprocessors such as the Intel 8085, the Zilog 280,
and the Motorola 6800/6809 were introduced based on second-generation microprocessors.
A third generation HMOs microprocessor, introduced in 1978 is typically represented by
the Intel 8086 and the Motorola 68000, which are 16-bit microprocessors.
During the 1980’s, fourth-generation HCMOS and BICMOS (a combination of
bipolar and HCMOS) 32-bit microprocessors evolved. Intel introduced the first commercial
32-bit microprocessor, the problematic Intel 432, which was eventually discontinued.
Since 1985, more 32-bit microprocessors have been introduced. These include Motorola’s
68020, 68030, 68040, 68060, PowerPC, Intel’s 80386, 80486, the Intel Pentium family,
Core Duo, and Core2 Duo microprocessors..
The performance offered by the 32-bit microprocessor is more comparable to
that of superminicomputers such as Digital Equipment Corporation’s VAX11/750 and
VAX11/780. Intel and Motorola also introduced RISC microprocessors: the Intel 80960
and Motorola 88 100/PowerPC, which had simplified instruction sets. Note that the purpose
of RISC microprocessors is to maximize speed by reducing clock cycles per instruction.
Almost all computations can be obtained from a simple instruction set. Note that, in order
to enhance performance significantly, Intel Pentium Pro and other succeeding members of
the Pentium family and Motorola 68060 are designed using a combination of RISC and
CISC.of the Motorola 68XXX and PowerPC microprocessors will
be provided next. Motorola’s 32-bit microprocessors based on the 68000 (16-bit
microprocessor) architecture include the MC68020, MC68030, MC68040, and MC68060.
Table 1.1 compares the basic features of some of these microprocessors with the 68000.
MC68020 is Motorola’s first 32-bit microprocessor. The design of the 68020 is
based on the 68000. The 68020 can perform a normal read or write cycle in 3 clock cycles
without wait states as compared to the 68000, which completes a read or write operation in
4 clock cycles without wait states. As far as the addressing modes are concerned, the 68020
includes new modes beyond those of the 68000. Some of these modes are scaled indexing,
larger displacements, and memory indirection.
Features of 32-bit and 64-bit Microprocessors
In this section we describe the basic aspects of typical 32- and 64-bit microprocessors.
Topics include on-chip features such as pipelining, memory management, floating-
point, and cache memory implemented in typical 32- and 64-bit microprocessors. The
first 32-bit microprocessor, Intel’s problematic iAPX432, was introduced in 1980. Soon
afterward, the concept of mainji-ame on a chip or micromainframe was used to indicate the
capabilities of these microprocessors and to distinguish them from previous 8- and 16-bit
microprocessors.
The introduction of several 32-bit microprocessors revolutionized the
microprocessor world. The performance of these 32-bit microprocessors is actually more
comparable to that of superminicomputers such as Digital Equipment Corporation’s
VAXl1/750 and VAX11/780. Designers of 32-bit microprocessors have implemented
many powerful features of these mainframe computers to increase the capabilities of
microprocessor chip sets: pipelining, on-chip cache memory, memory management, and
floating-point arithmetic.In pipelining, instruction fetch and execute cycles overlap. This method allows simultaneous preparation for execution of one or more instructions while another instruction is being executed. Pipelining was used for many years in mainframe and minicomputer CPUs to speed up the instruction execution time of these machines. The 32-bit microprocessors implement the pipelining concept and operate simultaneously on several 32-bit words, which may represent different instructions or part of a single instruction.
Although pipelining greatly increases the rate of execution of nonbranching code,
pipelines must be emptied and refilled each time a branch or jump instruction appears in
the code. This may slow down the processing rate for code with many branches or jumps.
Thus, there is an optimum pipeline depth, which is strongly related to the instruction set,
architecture, and gate density attainable on the processor chip.With memory management, virtual memory techniques, traditionally a feature of mainframes, are also implemented as on-chip hardware on typical 32-bit microprocessors.
This allows programmers to write programs much larger than those that could fit in the
main memory space available to microprocessors; the programs are simply stored on a
secondary device such as a hard disk, and portions of the program are swapped into main
memory as needed.Segmentation circuitry has been included in many 32-bit microprocessor chips.With this technique, blocks of code called segments, which correspond to modules of the
program and have varying sizes set by the programmer or compiler, are swapped. For many
applications, however, an alternative method borrowed from mainframes and superminis
calledpaging is used. Basically, paging differs from segmentation in that pages are of equal
size. Demandpaging, in which the operating system swaps pages automatically as needed,
can be used with all 32-bit microprocessors।
The 64-bit microprocessors such as Power PC 750 include all the features of 32-bit
microprocessors. In addition, they contain multiple on-chip integer and floating-point units
and a larger address and data buses. The 64-bit microprocessors can typically execute four
instructions per clock cycle and can run at a clock speed of over 2 GHz. The original Pentium
microprocessor is a CISC microprocessor. Pentium Pro and other succeeding members of
the Pentium family are designed using a combination of mostly microprogramming (CISC)
and some hardwired control (RISC) whereas the PowerPC is designed using hardwired
control with almost no microcode. The PowerPC is a RISC microprocessorand therefore
includes a simple instruction set. This instruction set includes register-to-register, load, and
store instructions. All instructions involving arithmetic operations use registers; load and
store instructions are utilized to access memory. Almost all computations can be obtained
from these simple instructions. Finally, 64-bit microprocessors are ideal candidates for
data-crunching machines and high-performance desktop systems and workstations.
Topics include on-chip features such as pipelining, memory management, floating-
point, and cache memory implemented in typical 32- and 64-bit microprocessors. The
first 32-bit microprocessor, Intel’s problematic iAPX432, was introduced in 1980. Soon
afterward, the concept of mainji-ame on a chip or micromainframe was used to indicate the
capabilities of these microprocessors and to distinguish them from previous 8- and 16-bit
microprocessors.
The introduction of several 32-bit microprocessors revolutionized the
microprocessor world. The performance of these 32-bit microprocessors is actually more
comparable to that of superminicomputers such as Digital Equipment Corporation’s
VAXl1/750 and VAX11/780. Designers of 32-bit microprocessors have implemented
many powerful features of these mainframe computers to increase the capabilities of
microprocessor chip sets: pipelining, on-chip cache memory, memory management, and
floating-point arithmetic.In pipelining, instruction fetch and execute cycles overlap. This method allows simultaneous preparation for execution of one or more instructions while another instruction is being executed. Pipelining was used for many years in mainframe and minicomputer CPUs to speed up the instruction execution time of these machines. The 32-bit microprocessors implement the pipelining concept and operate simultaneously on several 32-bit words, which may represent different instructions or part of a single instruction.
Although pipelining greatly increases the rate of execution of nonbranching code,
pipelines must be emptied and refilled each time a branch or jump instruction appears in
the code. This may slow down the processing rate for code with many branches or jumps.
Thus, there is an optimum pipeline depth, which is strongly related to the instruction set,
architecture, and gate density attainable on the processor chip.With memory management, virtual memory techniques, traditionally a feature of mainframes, are also implemented as on-chip hardware on typical 32-bit microprocessors.
This allows programmers to write programs much larger than those that could fit in the
main memory space available to microprocessors; the programs are simply stored on a
secondary device such as a hard disk, and portions of the program are swapped into main
memory as needed.Segmentation circuitry has been included in many 32-bit microprocessor chips.With this technique, blocks of code called segments, which correspond to modules of the
program and have varying sizes set by the programmer or compiler, are swapped. For many
applications, however, an alternative method borrowed from mainframes and superminis
calledpaging is used. Basically, paging differs from segmentation in that pages are of equal
size. Demandpaging, in which the operating system swaps pages automatically as needed,
can be used with all 32-bit microprocessors।
The 64-bit microprocessors such as Power PC 750 include all the features of 32-bit
microprocessors. In addition, they contain multiple on-chip integer and floating-point units
and a larger address and data buses. The 64-bit microprocessors can typically execute four
instructions per clock cycle and can run at a clock speed of over 2 GHz. The original Pentium
microprocessor is a CISC microprocessor. Pentium Pro and other succeeding members of
the Pentium family are designed using a combination of mostly microprogramming (CISC)
and some hardwired control (RISC) whereas the PowerPC is designed using hardwired
control with almost no microcode. The PowerPC is a RISC microprocessorand therefore
includes a simple instruction set. This instruction set includes register-to-register, load, and
store instructions. All instructions involving arithmetic operations use registers; load and
store instructions are utilized to access memory. Almost all computations can be obtained
from these simple instructions. Finally, 64-bit microprocessors are ideal candidates for
data-crunching machines and high-performance desktop systems and workstations.
Open Mobile Alliance (OMA)
The Open Mobile Alliance (OMA) was formed to promote global user adaptation of mobile services and applications by ensuring seamless interoperability. It was established on June 12, 2002. The work done by the Open Mobile Architecture and WAP fora laid the foundation of OMA. Later on Location Interoperability Forum (LIF), SyncML, Multi-Media Messaging Services Inter-Operability (MMS-IOP), Wireless Village, and Mobile Wireless Internet Forum (MWIF) joined the alliance by consolidating their efforts with the OMA. These fora were working individually in the same problem space of mobile services and applications. The LIF is promoting and working industry common solutions for the location based services. The SyncML is working on specifying an open standard for establishing a protocol between devices, applications and networks to ensure a consistent set of data available on any device or application at any time. The MMS-IOP is facilitating and coordinating MMS interoperability testing and problem solving. The Wireless Village is specifying the Internet based mobile instant messaging and presence services, all fully interoperable and leveraging existing web technologies. The MWIF was specifying an open mobile wireless and Internet architecture that is independent of the wireless access technology.
OMA harmonizes all these efforts and provides a common platform for the development of all these mobile services and applications.OMA is developing global open standards for services and applications independent of underlying wireless access technology, e.g. cdma2000, and WCDMA. It intends to provide seamless inter-technology and inter-generation roaming for services and applications across the globe. OMA has achieved its first milestone by developing specifications for OMA Download Feature Set.
The specification enables distribution and download of content data to mobile devices independent of vendor and content। It is an over the air protocol and features enhanced download reliability। The specification also provides protocols for associating Digital Rights Management (DRM) with content. DRM allows control of use and distribution of media content.OMA is a new organization compared to the other organizations discussed in this chapter, such as 3GPP, and 3GPP2. They have taken a mission that is very much needed to promote data services on wireless. OMA could play a key role in promoting the data over wireless in the future. The mobile services and applications is an important part of the wireless data industry, since it has direct interaction with the end users.
Development of this part can help boost wireless data usage। Currently, OMA is working on simplifying data application and content development for a mobile user. This includes work on the specifications related to the MMS. It is looking into providing a global standard for email notification on the wireless devices. OMA is working on script language for browsing environment. It is also working on the implementation of interoperability process and testing between its members.
IEEE 802
The Institute for Electrical and Electronic Engineers (IEEE) is a well-recognized body that was founded in 1884. The IEEE is a global technical, professional society serving the public interest and members in electrical, electronics, computer, information, and other technologies.The IEEE, which is based in the United States sponsors more than 300 conferences each year, including technical conferences, workshops, professional/careers/technical policy meetings, and standards working group meetings. In addition, the IEEE is involved in almost 200 "topical interest" meetings, either as consultants to the technical program or as nonfinancial partners.
The IEEE standards process consists of more than 30,000 volunteers and a Standards Board। IEEE is responsible for creating standards for the very popular local area networks (LAN) standards, such as 802.3 (also known as Ethernet), IEEE 802.5 (token ring), and 802.11 (wireless LAN).The standards process begins with the submission of a Project Authorization Request (PAR) to the Standards Board. According to IEEE, a PAR is the means by which standards projects are started. PARs define the scope, purpose, and contact points for the new project. If the Standards Board approves the PAR, then the standards process is initiated by the creation of a standards working group. The members of the standards working group are volunteers and may or may not be members of the IEEE.
The members of the IEEE working group create a draft standard. This draft is reviewed by a balloting group of IEEE members for review and approval. The constitution of the ballot group consists of standard's developers, potential users and others having general interest.Once this process is completed, the Standards Board conducts a review of the Final Draft Standard for the approval. Standards are typically reviewed once every five years for revision.One of the standards of interest to us is the IEEE 802 family, which is formally referred to as the IEEE 802 LAN/MAN Standards Committee. According to the IEEE, the IEEE 802 LAN/MAN Standards Committee develops local area network standards and metropolitan area network standards. The most widely used standards are for the Ethernet family, token ring, wireless LAN, bridging and virtual bridged LANs. An individual working group provides the focus for each area. IEEE 802 family standards and documents cover layers 1 and 2 of the OSI reference model.
This uses static encryption keys and does not have key distribution management। 802।11i will incorporate 802.1x that provides a framework for authenticating and controlling user traffic to a protected network. 802.1x provides dynamically varying encryption keys. It ties a protocol called Extensible Authentication Protocol (EAP) and provides multiple authentication methods, such as token cards, Kerberos, certificates, and public key authentication. 802.11i will use a stronger encryption algorithm such as Advanced Encryption Standard (AES). In summary, 802.11 task groups are exploring solutions for providing higher speed access, reduced interference, better quality management, strong security, and user roaming.
The IEEE standards process consists of more than 30,000 volunteers and a Standards Board। IEEE is responsible for creating standards for the very popular local area networks (LAN) standards, such as 802.3 (also known as Ethernet), IEEE 802.5 (token ring), and 802.11 (wireless LAN).The standards process begins with the submission of a Project Authorization Request (PAR) to the Standards Board. According to IEEE, a PAR is the means by which standards projects are started. PARs define the scope, purpose, and contact points for the new project. If the Standards Board approves the PAR, then the standards process is initiated by the creation of a standards working group. The members of the standards working group are volunteers and may or may not be members of the IEEE.
The members of the IEEE working group create a draft standard. This draft is reviewed by a balloting group of IEEE members for review and approval. The constitution of the ballot group consists of standard's developers, potential users and others having general interest.Once this process is completed, the Standards Board conducts a review of the Final Draft Standard for the approval. Standards are typically reviewed once every five years for revision.One of the standards of interest to us is the IEEE 802 family, which is formally referred to as the IEEE 802 LAN/MAN Standards Committee. According to the IEEE, the IEEE 802 LAN/MAN Standards Committee develops local area network standards and metropolitan area network standards. The most widely used standards are for the Ethernet family, token ring, wireless LAN, bridging and virtual bridged LANs. An individual working group provides the focus for each area. IEEE 802 family standards and documents cover layers 1 and 2 of the OSI reference model.
This uses static encryption keys and does not have key distribution management। 802।11i will incorporate 802.1x that provides a framework for authenticating and controlling user traffic to a protected network. 802.1x provides dynamically varying encryption keys. It ties a protocol called Extensible Authentication Protocol (EAP) and provides multiple authentication methods, such as token cards, Kerberos, certificates, and public key authentication. 802.11i will use a stronger encryption algorithm such as Advanced Encryption Standard (AES). In summary, 802.11 task groups are exploring solutions for providing higher speed access, reduced interference, better quality management, strong security, and user roaming.
IETF(Internet Engineering Yask Force).
The working and structure of IETF is different from a telecommunication standards body, such as 3GPP and 3GPP2. It is not driven by industry leaders, does not require membership or dues, and is open to any interested individual. This actually benefits the industry by opening up the platform for good ideas and opinions. At the same time, it makes the development of an open protocol slower compared to a telecom standards body.
The actual technical work of the IETF is done in its working groups (WGs), which are organized by topics into several areas. There are eight different areas in the IETF: application area, internet area, operations and management area, routing area, security area, sub-ip area, transport area, and user services area. Each WG has a charter and a set of work items. One chairperson (sometimes two), manages the WGs. The area directors (AD), who are collectively called IESGs, oversee the WGs. The WGs or areas are also overseen by the Internet Architecture Board (IAB), which is responsible for providing architectural oversight and focuses on long-range planning and coordination among the various areas. When members are interested in starting a new WG, they can form a "Birds of a Feather" (BOF) session. This is taken from the saying, "Birds of a feather flock together." If the BOF gathers sufficient interest and is thought to be working on a useful and solvable problem, a WG is formed.
WGs do most of their work using the e-mail distribution list. They meet three times a year for face-to-face meetings. Usually, a participant submits an Internet draft (ID) containing a solution for any of the WG's work items. The ID is discussed and its contents are agreed on by rough consensus. A WG may merge multiple solutions for different issues or the same issue into a WG ID. When all the issues are addressed, the WG chair calls for a last call for comments on the WG ID. After the comments are successfully addressed, the ID is sent to the IESG. The IESG also issues the last call for comments on the ID, but from all IETF participants. After all the comments are considered, the draft is sent to the request for comments (RFC) editor for publication as an RFC. RFCs are permanent IETF publications available as specifications to the users.
In addition to the liaisons and BOFs, there is a lot of focus inside IETF on developing protocols/recommendations that are also friendly to different wireless technology. Individuals from 3GPP, 3GPP2, Bluetooth, and the WLAN industry are working in different WGs to get solutions that would help in bringing IP to their technologies. Examples of such WGs are Performance Implications of Link Characteristics (PILC), Seamless Mobility (SEAMOBY), Session Initiation Protocol (SIP), Mobile Ad-Hoc Networks (MANET), Mobile IP, Zero Configuration Networks (ZeroConf), and Robust Header Compression (ROHC). This trend will increase due to the open nature of IETF.
The actual technical work of the IETF is done in its working groups (WGs), which are organized by topics into several areas. There are eight different areas in the IETF: application area, internet area, operations and management area, routing area, security area, sub-ip area, transport area, and user services area. Each WG has a charter and a set of work items. One chairperson (sometimes two), manages the WGs. The area directors (AD), who are collectively called IESGs, oversee the WGs. The WGs or areas are also overseen by the Internet Architecture Board (IAB), which is responsible for providing architectural oversight and focuses on long-range planning and coordination among the various areas. When members are interested in starting a new WG, they can form a "Birds of a Feather" (BOF) session. This is taken from the saying, "Birds of a feather flock together." If the BOF gathers sufficient interest and is thought to be working on a useful and solvable problem, a WG is formed.
WGs do most of their work using the e-mail distribution list. They meet three times a year for face-to-face meetings. Usually, a participant submits an Internet draft (ID) containing a solution for any of the WG's work items. The ID is discussed and its contents are agreed on by rough consensus. A WG may merge multiple solutions for different issues or the same issue into a WG ID. When all the issues are addressed, the WG chair calls for a last call for comments on the WG ID. After the comments are successfully addressed, the ID is sent to the IESG. The IESG also issues the last call for comments on the ID, but from all IETF participants. After all the comments are considered, the draft is sent to the request for comments (RFC) editor for publication as an RFC. RFCs are permanent IETF publications available as specifications to the users.
In addition to the liaisons and BOFs, there is a lot of focus inside IETF on developing protocols/recommendations that are also friendly to different wireless technology. Individuals from 3GPP, 3GPP2, Bluetooth, and the WLAN industry are working in different WGs to get solutions that would help in bringing IP to their technologies. Examples of such WGs are Performance Implications of Link Characteristics (PILC), Seamless Mobility (SEAMOBY), Session Initiation Protocol (SIP), Mobile Ad-Hoc Networks (MANET), Mobile IP, Zero Configuration Networks (ZeroConf), and Robust Header Compression (ROHC). This trend will increase due to the open nature of IETF.
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